Electrical components are commonly mounted on circuit panel structures such as circuit boards. Circuit panels ordinarily include a generally flat sheet of a dielectric material with electrical conductors disposed on a major, flat surface of the panel or on both major surfaces. The conductors are commonly formed from metallic materials such as copper and serve to interconnect the electrical components mounted to the board. Where the conductors are disposed on both major surfaces of the panel, the panel may have additional conductors extending through the dielectric layer so as to interconnect the conductors on opposite surfaces. Multi-layer circuit board assemblies have been made heretofore which incorporate plural, stacked circuit boards with additional layers of dielectric materials separating the conductors on mutually facing surfaces of adjacent boards in the stack. These multi-layer assemblies ordinarily incorporate interconnections extending between the conductors on the various circuit boards in the stack as necessary to provide the required electrical interconnections.
Electrical components which can be mounted to circuit panel structures include so-called "discrete" components and integrated circuits which include numerous components in a single chip. Chips of this nature can be mounted on elements commonly referred to as "chip carriers" which are specialized circuit panel structures. A chip carrier may be incorporated in a package which is mounted to a larger circuit board and interconnected with the remaining elements of the circuit. Alternatively, the chip can be mounted directly to the same circuit panel which carries other components of the system. This arrangement is ordinarily referred to as a "hybrid circuit". Relatively large circuit panels are commonly made of polymeric materials, typically with reinforcement such as glass, whereas very small circuit panels such as those used as semiconductor chip carriers may be formed from ceramics, silicon or the like.
There have been increasing needs for circuit panel structures which provide high density, complex interconnections. The needs have been particularly acute in the case of circuit panel structures for use as chip carriers or in hybrid circuits, but are also felt in other applications. These needs are addressed by multilayer circuit panel structures. The methods generally used to fabricate multi-layer panel structures have certain serious drawbacks. Multi-layer panels are commonly made by providing individual,. dual sided circuit panels with appropriate conductors thereon. The panels are then stacked one atop the other with one or more layers of uncured or partially cured dielectric material, commonly referred to as "prepregs" disposed between each pair of adjacent panels. Where an electrically conductive ground plane is desired between adjacent panels, the same may be formed by a layer of foil disposed between two prepregs, the foil and the prepreg being disposed between adjacent panels in the stack. Such a stack ordinarily is cured under heat and pressure to form a unitary mass. After curing, holes are drilled through the stack at locations where connections between different boards are desired. The resulting holes are then coated or filled with electrically conductive materials, typically by plating the interiors of the holes.
It is difficult to drill holes with a high aspect ratio or ratio of depth to diameter. The drills used to form the holes tend to deviate from a straight path as they pass through the various layers, leading to inaccuracies in placement of the holes. Moreover, there is always some misalignment between the various boards in the stack. Tolerance zones must be provided around the intended location of each hole in each panel to compensate for these factors. Small drills are prone to breakage and hence there is a practical lower limit on hole size. Additional difficulties are encountered in depositing conductive material within small holes of high aspect ratio. For all of these reasons, the holes used in assemblies fabricated according to these methods must be relatively large and hence consume substantial amounts of space in the assembly. Moreover, these holes necessarily extend from the top or bottom of the stack. Therefore, even where interconnections are not required in the top or bottom layers, space must be provided for holes to pass through these layers so as to provide needed interconnections in the middle layers. Accordingly, substantial amounts of the available surface area on the panels must be allocated to the holes and to accommodate the tolerance zones ground the holes. Moreover, the electrical interconnections formed by depositing conductive materials in such drilled holes tend to be weak and susceptible to failures induced by stresses encountered in service, including stresses caused by differential thermal expansion of the dielectric and conductive materials. The drilling method and the general nature of the laminates used therein is described, for example in Doherty, Jr., U.S. Pat. No. 3,793,469; and Guarracini, U.S. Pat. No. 3,316,618. Various alternative approaches have been proposed.
Parks et al., U.S. Pat. No. 3,541,222; Crepeau, U.S. Pat. No. 4,249,032; Luttmer, U.S. Pat. No. 3,795,037; Davies et al., U.S. Pat. No. 3,862,790 and Zifcak, U.S. Pat. No. 4,793,814 all relate generally to structures which have metallic or other conductive elements arranged at relatively closely spaced locations on a dielectric sheet with the conductive elements protruding through the dielectric sheet in both directions. Such a sheet may be sandwiched between a pair of circuit boards and the circuit boards may be clamped or otherwise held together so as to provide mechanical interengagement between conductive elements on the adjacent faces of the circuit boards and the conductive elements of the composite sheet. In each of these arrangements, the conductive elements, the composite sheet or both is resilient or malleable so as to provide for close interengagement between the conductive elements of the composite sheet and the conductors on the circuit boards. Although these arrangements provide interconnections of a fashion without drilling, they suffer from serious drawbacks including the need for extraneous mechanical elements to hold the assembly together, and limited reliability.
Beck, U.S. Pat. No. 3,616,532 describes a variant of this approach in which small coil springs coated with a fusible solder are mounted in insulating boards which are then stacked between printed circuit layers. The assembly is heated so as to melt the solder, thereby freeing the springs to expand into engagement with the conductors on adjacent boards so that the spring and solder cooperatively form an interconnection between the adjacent circuit boards. Dube et al., U.S. Pat. No. 3,509,270 utilizes a similar approach to connection of the two layers on opposite sides of the same circuit board, but in this case the spring may be allowed to expand through a layer of bonding material which holds the conductive layers to the opposite sides of the central board.
Dery et al., U.S. Pat. No. 4,729,809 discloses the use of an anisotropically conductive adhesive material disposed between opposing sublaminates, the adhesive composition having sufficient conductivity across the relatively small spaces between conductors on adjacent layers to form an electrical interconnection therebetween, but having low conductivity across the relatively large spaces between adjacent conductors on the same surface so that it does not produce an unwanted lateral interconnection along one surface. Boggs, U.S. Pat. No. 4,935,584 discloses an approach using multiple sublaminates or sheets, each having conductors on it and each having through holes. These sheets are laminated to one another in such fashion that some of the through holes are aligned with one another and conductive material is introduced into the aligned through holes to form a conductor extending in the vertical direction, between the various vertical levels of the assembly. Lemoine et al., U.S. Pat. No. 4,024,629 illustrates a generally similar approach in a multi-layer assembly of the types made from ceramic materials.
Phohofsky, U.S. Pat. No. 3,214,827 describes a technique in which plural circuit layers are stacked with apertures in the various layers being aligned, and an interconnecting element is physically advanced into the aligned apertures to form a vertical interconnect. Parks, U.S. Pat. No. 3,775,844 uses a multi-layer structure with interconnecting wafers some of which provide "z" access or vertical interconnections, the plural wafers in the stack being held together either by pressure or by fusing.
Pryor et al., U.S. Pat. No. 4,712,161 forms a multi-layer ceramic bodied circuit assembly with copper conductors on opposite sides of one element and with an interposer or vertical connector structure having solder or solid wire extending between opposite faces. The conductor bearing and vertical connection structures are stacked one atop the other so that the conductors are engaged with the vertical connections in the vertical connection structures. Each such structure has a layer of a fusible glass on its major surfaces. These structures are stacked and subjected to heat and pressure so that the fusible glass on the surfaces of the abutting structures, apparently with additional fusible glass interposed between these surfaces, fuse to join the entire assembly into a unitary multi-layer device. Jeannotte et al., U.S. Pat. No. 3,829,601 provides a multi-layer structure with the vertical interconnections formed by posts protruding vertically from the surfaces of the various layers, the posts being aligned with one another and bonded to one another by a metallurgical diffused interface. A separate insulating layer is disposed between the circuit bearing layers to insulate these from one another.
Berger et al., U.S. Pat. No. 4,788,766 uses conductor bearing circuit lamina having hollow, eyelet-like via structures, each such via structure having a rim protruding vertically from the surrounding structure. Each such via structure is provided with a thin layer of a conductive bonding material. In making the multi-layer structure, dielectric bonding films are interposed between the circuit bearing lamina. The dielectric films have apertures in locations corresponding to the locations of the eyelet structures, in the adjacent circuit bearing lamina. Thus, the upstanding rims of the eyelet structures can bear upon one another when the assembly is forced together under heat and pressure. The layers of conductive bonding material on the rims of the abutting eyelets are said to form bonds between the abutting eyelets structures. The dielectric bonding layer must necessarily be quite thin and the dielectric bonding layer must also have the holes in it at the specific locations required to form the interconnections. Further, each of these holes must be substantially larger than the eyelet rims. The tolerance of this system for deviations from planarity or paralleling, for misalignment between lamina and for misalignment between the lamina and the dielectric bonding films is limited. Moreover, only surface or point bonds are formed between abutting eyelet rims which tends to limit the strength of the vertical interconnections.
Ryan, U.S. Pat. No. 3,606,677 discloses a technique for making a multi-layer circuit board which relies upon controlled viscosity and flow characteristics of an adhesive bonding agent between layers to prevent the adhesive from penetrating into through holes within the layers. Abolafia et al., U.S. Pat. No. 3,795,047 uses circuit bearing laminates have epoxy coated thereon in a pattern corresponding to the pattern of the vertical interconnects. Conductive spherical particles are applied and held on this epoxy and form junctions with opposing layers when multiple layers are pressed together. Reid, U.S. Pat. No. 4,216,350 and Grabbe, U.S. Pat. No. 4,642,889 utilize sheet like interposers having multiple holes extending through them. Such holes are filled or partially filled with solder, with or without additional conductive material such as wire, and the interposer is then disposed between components to be connected and heated so as to form a plurality of soldered joints simultaneously. Bohrer et al., U.S. Pat. No. 3,077,511 utilizes a similar approach for connecting multiple layers of a printed circuit. In this case, the solder bearing interposer includes a dielectric film which apparently remains in place after the solder is fused.
Despite all of these efforts toward manufacture of multi-layer laminar electrical circuits, there have still been needs for further improvements in such circuits and in the materials and components used to manufacture the same.